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[VHDL-FPGA-Verilog] VGA

Description: 使用标准VHDL实现的VGA协议，可在CPLD或者FPGA上实现视频扩展-use VHDL to implement VGA protocol, which can be used in CPLD or FPGA.
Platform: | Size: 365568 | Author: 林铎 | Hits:

[Other] LCD1602_show

Description: CPLD 240T100 的lcd1602程序 是vhdl语言-CPLD 240T100 of lcd1602 program is vhdl language
Platform: | Size: 181248 | Author: 花无香 | Hits:

[VHDL-FPGA-Verilog] submit

Description: 用VHDL实现的双人飞机大战。支持PS/2和蜂鸣器。 需要两个CPLD核心协同完成。 含最终效果视频-Multiplayer air fight implemented in VHDL. PS/2 and beeper supported. Two CPLD cores are required to run this demo. Final video includes.
Platform: | Size: 13689856 | Author: | Hits:

[VHDL-FPGA-Verilog] decoder38

Description: 38译码器源码VHDL版， cpld EPM570版-38 decoder VHDL source code version
Platform: | Size: 114688 | Author: HAM | Hits:

[VHDL-FPGA-Verilog] syn_cnter_4

Description: 四位计数器，VHDL版，基于cpld EPM570芯片-The four bit counter, VHDL version, EPM570 chip based on CPLD
Platform: | Size: 157696 | Author: HAM | Hits:

[VHDL-FPGA-Verilog] EP2C5T144_VGA

Description: VGA EP2C5T altera QuartusII VHDL FPGA CPLD passed
Platform: | Size: 1696768 | Author: 寒雪亮 | Hits:

[VHDL-FPGA-Verilog] TEXIO

Description: TEXIO study testbench passed VHDL FPGA CPLD simulation Altera quartus
Platform: | Size: 53248 | Author: 寒雪亮 | Hits:

[VHDL-FPGA-Verilog] shuzizhong

Description: 基于CPLD的智能数字时钟VHDL设计，能实现时钟、秒表、闹钟、定时等功能-ntelligent digital clock CPLD VHDL-based design enables the clock, stopwatch, alarm clock, timer, and other functions
Platform: | Size: 411648 | Author: Steve | Hits:

[VHDL-FPGA-Verilog] hpi

Description: 用CPLD实现4个C6201通过HPI接口互连的逻辑设计，包含VHDL程序-4 of C6201s through the HPI interface logic design of interconnection with CPLD, including the VHDL program
Platform: | Size: 3864576 | Author: 郭玉东 | Hits:

[VHDL-FPGA-Verilog] szz

Description: 基于CPLD的数字钟，用VHDL语言编写，数码管显示，可调时调分，具有整点报时功能。-CPLD-based digital clock, using VHDL language, the digital display, an adjustable transfer points, the whole point timekeeping function.
Platform: | Size: 293888 | Author: 李襄 | Hits:

[VHDL-FPGA-Verilog] pinlvji

Description: 频率计 测量范围1-100MHz 测量阈值0.1s 计数部分为FPGA/CPLD 语言VHDL 显示部分为51 单片机加八位数码管 语言C-Frequency meter Measuring range 1-100 MHZ Measure threshold is 0.1 s Count part of FPGA/CPLD Language VHDL Display part of 51 MCU with eight digital tube Language C
Platform: | Size: 553984 | Author: 冉凯 | Hits:

[VHDL-FPGA-Verilog] yimaqi38

Description: 基于CPLD的38译码器程序设计，使用VHDL语言编程，38译码器显示在数码管上。-CPLD programming decoder 38 based on the use of VHDL language programming, the decoder 38 is displayed on the digital tube.
Platform: | Size: 131072 | Author: 孙大幕 | Hits:

[VHDL-FPGA-Verilog] liushuideng

Description: 基于CPLD的流水灯实现，使用VHDL语言编程，闪烁间隔为0.5秒。-CPLD-based water lights to achieve using VHDL language programming, blinking interval of 0.5 seconds.
Platform: | Size: 57344 | Author: 孙大幕 | Hits:

[VHDL-FPGA-Verilog] honglvdeng

Description: 基于CPLD的交通信号灯的实现，使用VHDL语言，使用不同颜色的二极管分别代表红黄绿三种信号灯。在数码管上可以分别显示倒计时。-CPLD-based implementation of the traffic lights, the use of VHDL language, using different colors of red yellow and green diodes representing three kinds of lights. On the digital countdown can be displayed separately.
Platform: | Size: 1085440 | Author: 孙大幕 | Hits:

[VHDL-FPGA-Verilog] bujinji-(kuozhan)

Description: 基于CPLD的步进电机控制实现，使用VHDL语言进行编程，通过控制开关，可以实现正转快速，正转慢速，反转快速，反转慢速四种不同的状态。- Based on CPLD stepper motor control implementation using VHDL language programming, by controlling the switch, you can achieve fast forward, slow forward, fast reverse, reverse slow four different states.
Platform: | Size: 74752 | Author: 孙大幕 | Hits:

[VHDL-FPGA-Verilog] dianzhen

Description: 基于CPLD的实现控制8x8点阵动态显示字母的程序，使用VHDL语言，通过调节分频系数可以实现点阵的变换速度，通过改变不同的状态可以让点阵显示不同的图案。- Based on CPLD for control 8x8 dot matrix dynamic display of letters, the use of VHDL language, by adjusting the division ratio can be achieved by changing the speed dot matrix by changing the different states allows dot matrix display different patterns.
Platform: | Size: 264192 | Author: 孙大幕 | Hits:

[VHDL-FPGA-Verilog] segsweep

Description: VHDL 驱动数码管 使用quartues 2编程使用CPLD驱动八段数码管-VHDL seg
Platform: | Size: 198656 | Author: jack | Hits:

[Windows Develop] 基于Quartus-II-的FPGACPLD开发

Description: 基于Quartus-II-的FPGACPLD开发(Development of FPGACPLD based on Quartus-II)
Platform: | Size: 6297600 | Author: VVVX | Hits:

[VHDL-FPGA-Verilog] xapp502配置例程

Description: FPGA配置例程，VHDL语言，使用CPLD对FPGA进行配置(The FPGA configuration routine, VHDL language, using CPLD on the FPGA configuration)
Platform: | Size: 18432 | Author: xiaohu111 | Hits:

[matlab] LDPC码编译码算法的研究与实现_李会雅

Description: 本文首先介绍了几种LDPC码的编译码算法，同时推导了译码错误概率和密度进化 过程，讨论了信道参数的门限效应。接着对LDPC码二分图中长度为4的环进行了深入 研究，提出了一种LDPC码校验矩阵的消4一环生成算法，采用Matlab和VC++融合编程 方式，完成了此算法的程序设计。此算法不仅可生成二进制LDPC码的校验矩阵，并且 对算法修正后，也可生成多进制LDPC码的校验矩阵。采用此算法后可避免LDPC码译 码过程中的重复迭代，显著提高了短帧LDPC码的误比特率性能。同时对不同参数对 LDPC码性能的影响进行了仿真，得到了一些结论。最后，利用VHDL语言在复杂可编 程逻辑器件(CPLD)上完成了LDPC码编码器的硬件实现。另外，给出了LDPC码译 码器硬件实现的整体结构图，结合对数似然比域内的置信传播迭代译码(LLR-BP)算 法，对译码器的各个模块进行了详细阐述。(Research and implementation of LDPC coding and decoding technology)
Platform: | Size: 1247232 | Author: 斯蓝蓝 | Hits:
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